Synthesis tools can recognize and encode Verilog HDL and VHDL state machines
during synthesis. This section presents guidelines to ensure the best results when you
use state machines. Ensuring that your synthesis tool recognizes a piece of code as a
state machine allows the tool to recode the state variables to improve the quality of
results, and allows the tool to use the known properties of state machines to optimize
other parts of the design. When synthesis recognizes a state machine, it is often able to
improve the design area and performance.
To achieve the best results _disibledevent=> else next_state <= state + 1;
end
1: begin
...
endcase
■ No state machine is inferred in the Quartus II software if the state variable is an
output.
■ No state machine is inferred in the Quartus II software for signed variables.
可以在Signal Tab II中观察是否被综合成状态机
非状态机 
状态机 
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